Basic MIPS Instructions

These are the assembly language statements covered in these notes that each directly correspond to one machine language instruction. There are additional basic assembly language statements that are not covered in these notes.

When pseudoinstructions are enabled, many of these instructions also correspond to pseudoinstructions that have greater flexibility in the arguments that they allow.

 

InstructionOperandsDescription
addd,s,t
d <-- s+t ; with overflow trap
addud,s,t
d <-- s+t ; without overflow trap
addid,s,const
d <-- s+const ; with overflow trap
      const is 16-bit two's comp
addiud,s,const
d <-- s+const ; without overflow trap
      const is 16-bit two's comp
andd,s,t
d <-- bitwise AND of s with t
andid,s,const
d <-- bitwise AND of s with const 
beqs,t,addr
branch if s == t
A branch delay slot follows the instruction.
bgezs,addr
Branch if the two's comp. integer
in register s is >= 0
A branch delay slot follows the instruction.
bltzs,addr
Branch if the two's comp. integer
in register s is < 0
A branch delay slot follows the instruction.
bnes,t,addr
branch if s != t
A branch delay slot follows the instruction.
divs,t
lo <-- s div t ; hi <-- s mod t
   two's comp. operands
divus,t
lo <-- s div t ; hi <-- s mod t
   unsigned operands
jtarget
after a delay of one machine cycle,
PC  <-- address of target 
lbd,off(b)
d <-- Sign-extended byte from 
      memory address b+off
  off is 16-bit two's complement
lbud,off(b)
d <-- Zero-extended byte 
      from memory address b+off
      off is 16-bit two's complement
lhd,off(b)
t <-- Sign-extended halfword 
      from memory address b+off
      off is 16-bit two's complement
lhud,off(b)
t <-- Zero-extended halfword 
      from memory address b+off
      off is 16-bit two's complement
luid,const
upper two bytes of $t <-- two byte const 
lower two bytes of $t <-- 0x0000 
lwd,off(b)
d <-- Word from memory address b+off
      off is 16-bit two's complement. 
mfhid
d <-- hi ;  Move From Hi
mflod
d <-- lo ;  Move From Lo
mults,t
hi / lo < -- s * t ;  two's comp operands 
multus,t
hi / lo < -- s * t ;  unsigned operands 
nord,s,$0
d <-- bitwise NOT of s
nord,s,t
d <-- bitwise NOR of s with t
ord,s,$0
d <-- s
ord,s,t
d <--bitwise OR of s with t 
orid,$0,const
d <-- zero-extended const
orid,s,const
d <-- s OR zero-extended const
sbd,off(b)
byte at off+b <-- low-order byte 
                  from register $d.
off is 16-bit two's complement 
shd,off(b)
two bytes at off+b <-- two low-order bytes 
                      from register $d.
off is 16-bit two's complement 
sll$0,$0,0
no operation
slld,s,shft
d <-- logical left shift of s by shft positions 
      where  0 <= shft < 32
sltd,s,t
if s < t
  d <-- 1
else
  d <-- 0

two's comp. operands 
sltid,s,imm
if s < imm
  d <-- 1
else
  d <-- 0

two's comp. operands 
sltiud,s,imm
if s < imm
  d <-- 1
else
  d <-- 0

unsigned operands 
sltud,s,t
if s < t
  d <-- 1
else
  d <-- 0

unsigned operands 
srad,s,shft
d <-- arithmetic right shift of s by shft positions 
      where  0 <= shft < 32
srld,s,shft
d <-- logical right shift of s by shft positions 
      where  0 <= shft < 32
subd,s,t
d <-- s - t; with overflow trap
subud,s,t
d <-- s - t; no overflow trap
swd,off(b)
Word at memory address (b+off) <-- $t
b is a register. off is 16-bit twos complement. 
xord,s,t
d <-- bitwise exclusive or of s with t
xorid,s,const
d <-- bitwise exclusive or of s with const 

 

 

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