8 QAM

8-QUADRATURE AMPLITUDE MODULATION(8-QAM):

• The amplitude gets changed in 8-QAM , and it is not a constant value.
• 3 bits encoded forming tribits and producing 8 different output phase.
• N = 3, M = 2^N = 2³ = 8
• Therefore 8 output phases will be produced.

8-QAM transmitter:

• The difference between 8-QAM and 8-PSK transmitter is the emission of invertor between C channel and Q product modulator.
• Input given to bit splitter where it is converted to parallel 3 channel output.
• It is inphase, quadrature control.
• The bit rate of 3 channel is f_b/3.
• I channel bit enters 2 to 4 level convertor.
• Q channel enters 2 to 4 level convertor. Where it converts parallel input digital to analog convertors(DAC).
• With 2 input bits 4 output combinations are possible.

Algorithm:

• I,Q – polarity

            Logic 1 – +1V

            Logic 0 – -1V

• C – magnitude

            Logic 1 – 1.307V

            Logic 0 – 0.541V

I	C
0	0	-0.541V
0	1	-1.307 V
1	0	+0.541V
1	1	+1.307V

Q	C
0	0	-0.541V
0	1	-1.307 V
1	0	+0.541V
1	1	+1.307V

Adjucent phase change by 1 bit and is called grade code (or) maximum distance code.

Bandwidth consideration:

Input data rate =f_b.

Data rate in I,Q channel = f_b /3.

Therefore fundamental frequency,

                                                f_a = (f_b /3) / 2

fa = fb /6

The output of BM = (X sin w_at) (sin w_ct)

wa = 2∏fbt/6

wc = 2∏fc

                              = {X sin 2∏f_bt/6 } {sin w_c = 2∏f_c }

                              = X/2 {cos 2∏ (f_c  – f_b/6 )t} -{cos 2∏ (f_c  + f_b/6 )t}

Therefore bandwidth,

                        BW= (f_c + f_b/6 ) – (f_c  – f_b/6 )

                               =2f_b/6

BW = fb/3

Q	I	C
0	0	0	-112.5
0	0	1	-157.5
0	1	0	-67.5
0	1	1	-22.5
1	0	0	112.5
1	0	1	157.5
1	1	0	67.5
1	1	1	22.5

8-QAM receiver:

• The power splitter directs to the input 8-QAM signal to I,Q channel product detectors and carrier recovery circuit.
• The incoming 8-QAM signal is mixed with the recovered carrier in the I product detector and quadrature carrier in Q product detector.
• The output of product detector(4 level PAM) is given to 4 to 2 level ADC’s.
• The output of ADC’s are I,C bits and Q,C’ bits .
• The parallel to serial logic circuit gives Q,C data stream bit.